module ADC128S102_Driver(
	clk,
	rst_n,
	conv_go,
	addr,
	conv_done,
	data,
	ADC_SCLK,
	ADC_CS_N,
	ADC_DIN,
	ADC_DOUT
);

	input clk;
	input rst_n;
	input conv_go;
	input [2:0] addr;
	output reg conv_done;
	output reg [11:0] data;
	output reg ADC_SCLK;
	output reg ADC_CS_N;
	output reg ADC_DIN;
	input ADC_DOUT;
	
	parameter CLOCK_FREQ = 50_000_000;
	parameter SCLK_FREQ = 12_500_000;
	parameter MCNT_DIV_CNT = CLOCK_FREQ/(SCLK_FREQ*2) - 1;
	
	reg [7:0] div_cnt;// 最小时间单位的定时计数器
	
	reg [5:0] lsm_cnt;// 序列计数器
	
	reg [11:0] data_r;// 序列机的执行单元
	reg [2:0] r_addr;
	
	reg conv_en;
	
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			div_cnt <= 0;
		else if(conv_en) begin
			if(div_cnt == MCNT_DIV_CNT)
				div_cnt <= 0;
			else
				div_cnt <= div_cnt + 1'd1;
		end
		else
			div_cnt <= 0;
	
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			lsm_cnt <= 0;
		else if(div_cnt == MCNT_DIV_CNT)begin
			if(lsm_cnt == 34)
				lsm_cnt <= 0;
			else
				lsm_cnt <= lsm_cnt + 1'd1;
		end else
			lsm_cnt <= lsm_cnt;
			
	always@(posedge clk)
		if(conv_go)
			r_addr <= addr;
		else
			r_addr <= r_addr;
	
	always@(posedge clk or negedge rst_n)
		if(!rst_n)begin
			data_r <= 12'd0;
			ADC_SCLK <= 1'd1;
			ADC_DIN <= 1'd1;
			ADC_CS_N <= 1'd1;
		end else begin
			case(lsm_cnt)
				0:begin ADC_CS_N <= 1'd1; ADC_SCLK <= 1'd1; end
				1:ADC_CS_N <= 1'd0;
				2:ADC_SCLK <= 1'd0;
				3:ADC_SCLK <= 1'd1;
				4:ADC_SCLK <= 1'd0;
				5:ADC_SCLK <= 1'd1;
				6:begin ADC_SCLK <= 1'd0; ADC_DIN <= r_addr[2]; end
				7:ADC_SCLK <= 1'd1;
				8:begin ADC_SCLK <= 1'd0; ADC_DIN <= r_addr[1]; end
				9:ADC_SCLK <= 1'd1;
				10:begin ADC_SCLK <= 1'd0; ADC_DIN <= r_addr[0]; end
				11:begin ADC_SCLK <= 1'd1; data_r[11] <= ADC_DOUT; end
				12:ADC_SCLK <= 1'd0;
				13:begin ADC_SCLK <= 1'd1; data_r[10] <= ADC_DOUT; end
				14:ADC_SCLK <= 1'd0;
				15:begin ADC_SCLK <= 1'd1; data_r[9] <= ADC_DOUT; end
				16:ADC_SCLK <= 1'd0;
				17:begin ADC_SCLK <= 1'd1; data_r[8] <= ADC_DOUT; end
				18:ADC_SCLK <= 1'd0;
				19:begin ADC_SCLK <= 1'd1; data_r[7] <= ADC_DOUT; end
				20:ADC_SCLK <= 1'd0;
				21:begin ADC_SCLK <= 1'd1; data_r[6] <= ADC_DOUT; end
				22:ADC_SCLK <= 1'd0;
				23:begin ADC_SCLK <= 1'd1; data_r[5] <= ADC_DOUT; end
				24:ADC_SCLK <= 1'd0;
				25:begin ADC_SCLK <= 1'd1; data_r[4] <= ADC_DOUT; end
				26:ADC_SCLK <= 1'd0;
				27:begin ADC_SCLK <= 1'd1; data_r[3] <= ADC_DOUT; end
				28:ADC_SCLK <= 1'd0;
				29:begin ADC_SCLK <= 1'd1; data_r[2] <= ADC_DOUT; end
				30:ADC_SCLK <= 1'd0;
				31:begin ADC_SCLK <= 1'd1; data_r[1] <= ADC_DOUT; end
				32:ADC_SCLK <= 1'd0;
				33:begin ADC_SCLK <= 1'd1; data_r[0] <= ADC_DOUT; end
				34:begin ADC_SCLK <= 1'd1; ADC_CS_N <= 1'd1; end
				default:ADC_CS_N <= 1'd1;
			endcase
		end
		
		always@(posedge clk or negedge rst_n)
			if(!rst_n)begin
				data <= 0;
				conv_done <= 0;
			end else if(lsm_cnt == 34 && div_cnt == MCNT_DIV_CNT) begin
				conv_done <= 1;
				data <= data_r;
			end else begin
				data <= data;
				conv_done <= 0;
			end
			
		always@(posedge clk or negedge rst_n)
			if(!rst_n)
				conv_en <= 0;
			else if(conv_go)
				conv_en <= 1;
			else if(lsm_cnt == 34 && div_cnt == MCNT_DIV_CNT)
				conv_en <= 0;
			else
				conv_en <= conv_en;
		
endmodule
